1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of controlling the same and, for example, to a memory device which nonvolatilely stores information and has an error correction circuit, and a method of controlling the memory device.
2. Description of the Related Art
In some kinds of nonvolatile memory devices, the state of the physical quantity that controls data storage changes along with the elapse of time. If the elapsed time has reached a predetermined length, the data may be lost. There are various types of memory devices having such a characteristic feature. One of such memory devices is, e.g., a nonvolatile semiconductor memory device which uses transistors having a so-called laminated gate structure as memory cells.
The laminated gate structure includes a tunnel insulating film, floating gate electrode, inter-electrode insulating film, and control gate electrode which are sequentially stacked on a substrate. To store information in a memory cell, electrons are injected from the substrate to the floating gate electrode through the tunnel insulating film. The electric charges accumulated in the floating gate electrode retain information. The electric charges accumulated in the floating gate electrode leak to the substrate through the tunnel insulating film as the time elapses. For this reason, the information retained in the memory cell can be lost along with the elapse of time (an error can occur in the information).
If the elapsed time from the information storage time is short, an error can rarely occur in the information. On the other hand, if a long time has elapsed after information storage, an error may occur in the information at a high probability. A memory device having a plurality of such memory cells sometimes includes an error correction mechanism for restoring erroneous information to a correct state.
Generally, to correct a number of errors which are contained in data formed from a plurality of bits due to, e.g., the elapse of time from information recording, a correction mechanism having a high error correction capability is necessary. A correction mechanism with a high error correction capability has a large circuit scale and requires high power consumption and a long time for processing. Normally, to guarantee to restore correct information even after the elapse of a long time from information storage, a memory device uses a correction mechanism having a high error correction capability. The high-performance error correction mechanism is applied equally regardless of the length of the elapsed time from information storage.
For this reason, even in reading information which has been stored for only a short time, the high-performance error correction mechanism is used. Since the information to be read contains not so many errors, the use of the high-performance error correction mechanism is wasteful. This leads to a waste of power in the memory device.
To increase the error correction capability, generally, the size of the error correction target information needs to be large. For example, an error-correcting code is generated not for 512-byte data but for, e.g., 4-kbyte data obtained by concatenating a plurality of 512-byte data. This increases the error correction capability. In this method, however, it is necessary to always read out 4-kbyte data even in reading out 512-byte data. This also results in a waste of power in the memory device.
Prior-art reference information related to this application is
JP-A 63-275225 (KOKAI)
In the reference, a correction apparatus which has a high error correction capability is disclosed.